1. Field of the Invention
The present invention relates in general to blanker driver system and method for beams such as particle or other beams. It more particularly relates to a blanker driver system and method, which may be used for systems such as particle beam lithography.
2. Background Art
There is no admission that the background art disclosed in this section legally constitutes prior art.
In a particle beam based pattern writing system, the writing process involves exposing a sample to the beam. A mechanism of blanking the beam is incorporated for situations in which it is required that the sample not be exposed to the beam. The writing process typically involves executing a sequence of consecutive exposure intervals, synchronized to a master clock. During each of the exposure intervals, the beam may be blanked or exposed for a programmable period of time. Precise, high resolution control of the exposure time within each interval is required in order to ensure high fidelity of the written pattern. High resolution delay lines, combined with appropriate logic circuitry are typically used to implement such timing control circuitry. However, this approach has several disadvantages, such as overcoming the inherent asynchronous delay associated with such devices, as well as the limited ability to scale such an implementation to medium-high speed clock rates, e.g. on the order of 1 GHz master clock frequency.
Variable-width pulses in a system with fixed interval timing can be generated by using a high frequency clock, whose period is much shorter than the fixed interval period, in combination with some counter logic. The logic can be programmed to provide an output pulse of a width equivalent to a programmable number of periods of the high-frequency clock. This approach does not extend to high resolution pulse width control, e.g. in order to achieve a timing resolution such as a 2.5 picoseconds timing resolution, because a high-frequency clock of 400 GHz would be required, and would be impractical.
At higher frequencies, delay lines are typically used, again in conjunction with some gating logic. The reference exposure clock can be combined with a delayed version of itself to generate a variable width pulse. A typical example of the use of delay lines is shown in FIG. 1.
Commercially available programmable delay lines are available with resolution on the order of 10 picoseconds steps. However there are several problems with this approach.
In a pattern writing instrument, successive exposure times are independently variable. Thus a programmable delay line device used in the manner described above must be reprogrammed between exposure clocks. Considering the various timing considerations associated with this programming process (setup, hold, and propagation delay of several nanoseconds) it is clear that a single delay line cannot be used to generate arbitrarily programmable delays on successive clock cycles. Thus a “ping-ponging” approach must be used with appropriate logic to switch between alternate delay lines. Furthermore, the number of additional delay lines required depends on the absolute delay through the device compared to the exposure clock period.
Resolution of 10 picoseconds is inadequate to achieve the level of exposure timing control required in the next generation of high speed mask writing instruments. For example if the exposure clock period is 2.5 nanoseconds, and a Minimum Blanking Interval between successive exposures is 20%, then 0.5 nanoseconds is reserved, and the resolution of exposure control using a typical state-of-the-art delay line would be 10 picoseconds/2.0 nanoseconds which equals 1 part in 200, or 0.5%. Performance targets for the next generation of high speed mask writing instruments indicate that this is inadequate.
The minimum absolute delay through a typical delay line device is on the order of several nanoseconds. In a synchronous system with a master exposure clock, special timing adjustments must be made in order to compensate for this asynchronous minimum delay through the device. Furthermore, if multiple delay line devices are required, as indicated above, then part-to-part skew must also be calibrated out.
As gating logic is required to combine the leading edge of one signal with the falling edge of another in order to generate the variable pulse-width (FIG. 1), the output pulse-width is susceptible to timing jitter between the two different paths taken prior to combination.
A problem exists in creating blanking signals for the beam of a particle beam column when increasing the flash rate for the next generation of beam lithography devices. A system and method is needed to create the blanking circuit to overcome these difficulties.